parent nodes: ErkanIsa

Power density images for a multi-standard IO cell operating @ 300 MHz

I was fooling around with a tool that I developed to extract the power density images for a given layout block. Below are the extracted images which show clearly where most of the current is flowing.

Total development time for the tool was approximately 3 hours and voila...for any design I can get now those fancy images which can help spotting bottlenecks. The images below represent more or less the initial condition of the system. For the real thermal images I still have to spice in a little thermodynamics including the package.

The IO was also designed by me. Unfortunately, most of the information is proprietary; hence, I publish only the art part :-)!



Last update: 08/04/2013 03:49